The present invention relates to a semiconductor device, and in particular, relates to a technique effective in application to a semiconductor device including an antenna switch.
Japanese Unexamined Patent Publication No. 2006-165224 describes a technique for providing a field effect transistor capable of potential stabilization between multi-gates without increasing insertion loss. More specifically, the field effect transistor has two ohmic electrodes formed over a semiconductor substrate, at least two gate electrodes disposed between the two ohmic electrodes, and a conductive region interposed between adjacent gate electrodes. The conductive region has a wide region, at one end thereof, which is wider than the conductive region interposed between the adjacent gate electrodes, so that the distance between the adjacent gate electrodes is smaller than the width of the wide region. Further, a resistance is coupled in series between the two ohmic electrodes through the wide region.